// Generator : SpinalHDL v1.10.2a    git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935
// Component : ftsdc010_sim

`timescale 1ns/1ps

module ftsdc010_sim (
  output wire          sdio_clk,
  inout  wire [0:0]    sdio_cmd,
  inout  wire [3:0]    sdio_dat,
  input  wire          apb_psel,
  input  wire [31:0]   apb_addr,
  input  wire [31:0]   apb_pwdata,
  output wire [31:0]   apb_prdata,
  input  wire          apb_pwrite,
  input  wire          apb_ptran,
  output wire          apb_pready_o,
  input  wire          clk,
  input  wire          reset
);

  wire                sdio_io_mmc_init;
  wire       [7:0]    sdio_io_sdio_clkdiv;
  wire                sdio_io_sdio_dat_en;
  wire                sdio_io_sdio_dat_write;
  wire                sdio_io_timeout_reset;
  wire                send_fifo_io_flush;
  wire                recv_fifo_io_flush;
  wire                sdio_io_sdio_clk;
  wire       [255:0]  sdio_io_sdio_rsp;
  wire                sdio_io_recv_stream_valid;
  wire       [31:0]   sdio_io_recv_stream_payload;
  wire                sdio_io_send_stream_ready;
  wire                sdio_io_busy;
  wire                sdio_io_cmd_send_done;
  wire                sdio_io_crc_rsp_ok;
  wire                sdio_io_crc_dat_ok;
  wire                sdio_io_crc_rsp_fail;
  wire                sdio_io_crc_dat_fail;
  wire                sdio_io_timeout;
  wire                sdio_io_timeout_rsp;
  wire                sdio_io_timeout_dat;
  wire                sdio_io_dat_end;
  wire                sdio_io_debug_flg;
  wire                send_fifo_io_push_ready;
  wire                send_fifo_io_pop_valid;
  wire       [31:0]   send_fifo_io_pop_payload;
  wire       [6:0]    send_fifo_io_occupancy;
  wire       [6:0]    send_fifo_io_availability;
  wire                recv_fifo_io_push_ready;
  wire                recv_fifo_io_pop_valid;
  wire       [31:0]   recv_fifo_io_pop_payload;
  wire       [6:0]    recv_fifo_io_occupancy;
  wire       [6:0]    recv_fifo_io_availability;
  wire       [30:0]   _zz_block_size;
  wire       [31:0]   _zz_send_stream_payload;
  wire       [31:0]   _zz_send_stream_payload_1;
  wire       [31:0]   _zz_send_stream_payload_2;
  wire       [31:0]   _zz_send_stream_payload_3;
  wire       [31:0]   _zz_when_ftsdc010_l252;
  wire       [31:0]   _zz_dat_remaining;
  wire       [31:0]   _zz_when_ftsdc010_l258;
  wire       [31:0]   _zz_dat_remaining_1;
  wire       [31:0]   _zz_send_payload;
  wire       [31:0]   _zz_send_payload_1;
  wire       [31:0]   _zz_send_payload_2;
  wire       [31:0]   _zz_send_payload_3;
  reg        [31:0]   cmd;
  reg        [31:0]   argu;
  wire       [31:0]   rsp0;
  wire       [31:0]   rsp1;
  wire       [31:0]   rsp2;
  wire       [31:0]   rsp3;
  reg        [31:0]   rsp_cmd;
  reg        [31:0]   dcr;
  reg        [31:0]   dtr;
  reg        [31:0]   dlr;
  wire       [31:0]   status;
  reg        [31:0]   clr;
  reg        [31:0]   int_mask;
  reg        [31:0]   pcr;
  reg        [31:0]   ccr;
  reg        [31:0]   bwr;
  reg        [31:0]   dwr;
  wire       [31:0]   rev;
  reg        [31:0]   feature;
  wire                recv_stream_valid;
  wire                recv_stream_ready;
  wire       [31:0]   recv_stream_payload;
  reg        [31:0]   prdata;
  wire       [5:0]    addr;
  wire       [5:0]    sdio_cmd_1;
  wire                sdio_cmd_need_rsp;
  wire                sdio_cmd_long_rsp;
  wire                sdio_cmd_app_cmd;
  wire                sdio_cmd_en;
  reg                 sdio_sdc_rst;
  wire                sdio_mmc_int_stop;
  wire                sdio_bus_4bit;
  wire                clr_rsp_crc_fail;
  wire                clr_dat_crc_fail;
  wire                clr_rsp_timeout;
  wire                clr_dat_timeout;
  wire                clr_rsp_crc_ok;
  wire                clr_dat_crc_ok;
  wire                clr_cmd_send;
  wire                clr_dat_end;
  reg        [31:0]   dat_remaining;
  wire                dma_en;
  wire       [15:0]   block_size;
  wire       [15:0]   one_value;
  wire                _zz_io_timeout_reset;
  reg                 _zz_io_timeout_reset_1;
  wire                _zz_io_timeout_reset_2;
  reg                 _zz_io_timeout_reset_3;
  reg                 cmd_en_trg;
  reg                 cmd_en;
  wire                send_stream_valid;
  wire                send_stream_ready;
  wire       [31:0]   send_stream_payload;
  reg                 send_valid;
  reg        [31:0]   send_payload;
  wire                dwr_read;
  wire                dwr_writ;
  wire       [31:0]   recv_stream_data;
  reg                 dwr_read_regNext;
  reg                 _zz_status;
  wire                _zz_when_ftsdc010_l8;
  reg                 _zz_when_ftsdc010_l8_1;
  wire                when_ftsdc010_l8;
  reg                 toplevel_sdio_io_crc_rsp_fail_regNext;
  wire                when_ftsdc010_l10;
  reg                 _zz_status_1;
  wire                _zz_when_ftsdc010_l8_2;
  reg                 _zz_when_ftsdc010_l8_3;
  wire                when_ftsdc010_l8_1;
  reg                 toplevel_sdio_io_crc_dat_fail_regNext;
  wire                when_ftsdc010_l10_1;
  reg                 _zz_status_2;
  wire                _zz_when_ftsdc010_l8_4;
  reg                 _zz_when_ftsdc010_l8_5;
  wire                when_ftsdc010_l8_2;
  reg                 toplevel_sdio_io_timeout_rsp_regNext;
  wire                when_ftsdc010_l10_2;
  reg                 _zz_status_3;
  wire                _zz_when_ftsdc010_l8_6;
  reg                 _zz_when_ftsdc010_l8_7;
  wire                when_ftsdc010_l8_3;
  reg                 toplevel_sdio_io_timeout_dat_regNext;
  wire                when_ftsdc010_l10_3;
  reg                 _zz_status_4;
  wire                _zz_when_ftsdc010_l8_8;
  reg                 _zz_when_ftsdc010_l8_9;
  wire                when_ftsdc010_l8_4;
  reg                 toplevel_sdio_io_crc_rsp_ok_regNext;
  wire                when_ftsdc010_l10_4;
  reg                 _zz_status_5;
  wire                _zz_when_ftsdc010_l8_10;
  reg                 _zz_when_ftsdc010_l8_11;
  wire                when_ftsdc010_l8_5;
  reg                 toplevel_sdio_io_crc_dat_ok_regNext;
  wire                when_ftsdc010_l10_5;
  reg                 _zz_status_6;
  wire                _zz_when_ftsdc010_l8_12;
  reg                 _zz_when_ftsdc010_l8_13;
  wire                when_ftsdc010_l8_6;
  reg                 toplevel_sdio_io_cmd_send_done_regNext;
  wire                when_ftsdc010_l10_6;
  wire                _zz_when_ftsdc010_l10;
  reg                 _zz_status_7;
  wire                _zz_when_ftsdc010_l8_14;
  reg                 _zz_when_ftsdc010_l8_15;
  wire                when_ftsdc010_l8_7;
  reg                 _zz_when_ftsdc010_l10_1;
  wire                when_ftsdc010_l10_7;
  reg        [31:0]   _zz_status_8;
  reg        [31:0]   cmd_ret;
  reg                 sdc_rst;
  wire                _zz_when_ftsdc010_l190;
  reg                 _zz_when_ftsdc010_l190_1;
  wire                when_ftsdc010_l190;
  reg                 toplevel_sdio_io_cmd_send_done_regNext_1;
  wire                when_ftsdc010_l194;
  reg        [31:0]   read_data;
  reg                 block_next;
  reg                 dat_trg;
  reg                 sdio_sdc_rst_regNext;
  reg                 cmd_en_trg_regNext;
  wire                when_ftsdc010_l240;
  reg                 dat_trg_regNext;
  wire                when_ftsdc010_l245;
  wire                when_ftsdc010_l252;
  wire                when_ftsdc010_l258;
  reg                 toplevel_sdio_io_dat_end_regNext;
  wire                when_ftsdc010_l249;
  wire                when_ftsdc010_l273;
  wire                when_ftsdc010_l275;
  wire                when_ftsdc010_l294;
  wire                when_ftsdc010_l316;
  function [31:0] zz_feature(input dummy);
    begin
      zz_feature = 32'h0;
      zz_feature[7 : 0] = 8'h40;
    end
  endfunction
  wire [31:0] _zz_1;

  assign _zz_block_size = ({{15{one_value[15]}},one_value} <<< dcr[3 : 0]);
  assign _zz_send_stream_payload = apb_pwdata;
  assign _zz_send_stream_payload_1 = apb_pwdata;
  assign _zz_send_stream_payload_2 = apb_pwdata;
  assign _zz_send_stream_payload_3 = apb_pwdata;
  assign _zz_when_ftsdc010_l252 = {{16{block_size[15]}}, block_size};
  assign _zz_dat_remaining = {{16{block_size[15]}}, block_size};
  assign _zz_when_ftsdc010_l258 = {{16{block_size[15]}}, block_size};
  assign _zz_dat_remaining_1 = {{16{block_size[15]}}, block_size};
  assign _zz_send_payload = apb_pwdata;
  assign _zz_send_payload_1 = apb_pwdata;
  assign _zz_send_payload_2 = apb_pwdata;
  assign _zz_send_payload_3 = apb_pwdata;
  xsdio sdio (
    .io_sdio_clk            (sdio_io_sdio_clk                 ), //o
    .io_sdio_cmd            (sdio_cmd                         ), //~
    .io_sdio_dat            (sdio_dat                         ), //~
    .io_mmc_init            (sdio_io_mmc_init                 ), //i
    .io_sdio_cmd_en         (cmd_en                           ), //i
    .io_sdio_cmd_valu       (sdio_cmd_1[5:0]                  ), //i
    .io_sdio_cmd_argu       (argu[31:0]                       ), //i
    .io_sdio_cmd_need_rsp   (sdio_cmd_need_rsp                ), //i
    .io_sdio_cmd_long_rsp   (sdio_cmd_long_rsp                ), //i
    .io_sdio_rsp            (sdio_io_sdio_rsp[255:0]          ), //o
    .io_sdio_bus_4bit       (sdio_bus_4bit                    ), //i
    .io_sdio_clkdiv         (sdio_io_sdio_clkdiv[7:0]         ), //i
    .io_dat_next_en         (block_next                       ), //i
    .io_block_size          (block_size[15:0]                 ), //i
    .io_sdio_dat_en         (sdio_io_sdio_dat_en              ), //i
    .io_sdio_dat_write      (sdio_io_sdio_dat_write           ), //i
    .io_recv_stream_valid   (sdio_io_recv_stream_valid        ), //o
    .io_recv_stream_ready   (recv_fifo_io_push_ready          ), //i
    .io_recv_stream_payload (sdio_io_recv_stream_payload[31:0]), //o
    .io_send_stream_valid   (send_fifo_io_pop_valid           ), //i
    .io_send_stream_ready   (sdio_io_send_stream_ready        ), //o
    .io_send_stream_payload (send_fifo_io_pop_payload[31:0]   ), //i
    .io_timeout_tick        (dtr[31:0]                        ), //i
    .io_timeout_reset       (sdio_io_timeout_reset            ), //i
    .io_busy                (sdio_io_busy                     ), //o
    .io_cmd_send_done       (sdio_io_cmd_send_done            ), //o
    .io_crc_rsp_ok          (sdio_io_crc_rsp_ok               ), //o
    .io_crc_dat_ok          (sdio_io_crc_dat_ok               ), //o
    .io_crc_rsp_fail        (sdio_io_crc_rsp_fail             ), //o
    .io_crc_dat_fail        (sdio_io_crc_dat_fail             ), //o
    .io_timeout             (sdio_io_timeout                  ), //o
    .io_timeout_rsp         (sdio_io_timeout_rsp              ), //o
    .io_timeout_dat         (sdio_io_timeout_dat              ), //o
    .io_dat_end             (sdio_io_dat_end                  ), //o
    .io_debug_flg           (sdio_io_debug_flg                ), //o
    .clk                    (clk                              ), //i
    .reset                  (reset                            )  //i
  );
  StreamFifo send_fifo (
    .io_push_valid   (send_stream_valid             ), //i
    .io_push_ready   (send_fifo_io_push_ready       ), //o
    .io_push_payload (send_stream_payload[31:0]     ), //i
    .io_pop_valid    (send_fifo_io_pop_valid        ), //o
    .io_pop_ready    (sdio_io_send_stream_ready     ), //i
    .io_pop_payload  (send_fifo_io_pop_payload[31:0]), //o
    .io_flush        (send_fifo_io_flush            ), //i
    .io_occupancy    (send_fifo_io_occupancy[6:0]   ), //o
    .io_availability (send_fifo_io_availability[6:0]), //o
    .clk             (clk                           ), //i
    .reset           (reset                         )  //i
  );
  StreamFifo recv_fifo (
    .io_push_valid   (sdio_io_recv_stream_valid        ), //i
    .io_push_ready   (recv_fifo_io_push_ready          ), //o
    .io_push_payload (sdio_io_recv_stream_payload[31:0]), //i
    .io_pop_valid    (recv_fifo_io_pop_valid           ), //o
    .io_pop_ready    (recv_stream_ready                ), //i
    .io_pop_payload  (recv_fifo_io_pop_payload[31:0]   ), //o
    .io_flush        (recv_fifo_io_flush               ), //i
    .io_occupancy    (recv_fifo_io_occupancy[6:0]      ), //o
    .io_availability (recv_fifo_io_availability[6:0]   ), //o
    .clk             (clk                              ), //i
    .reset           (reset                            )  //i
  );
  assign rsp0 = 32'h0;
  assign rsp1 = 32'h0;
  assign rsp2 = 32'h0;
  assign rsp3 = 32'h0;
  assign rev = 32'h0;
  assign _zz_1 = zz_feature(1'b0);
  always @(*) feature = _zz_1;
  assign apb_pready_o = 1'b1;
  assign sdio_clk = sdio_io_sdio_clk;
  assign addr = apb_addr[7 : 2];
  assign apb_prdata = prdata;
  assign sdio_cmd_1 = cmd[5 : 0];
  assign sdio_cmd_need_rsp = cmd[6];
  assign sdio_cmd_long_rsp = cmd[7];
  assign sdio_cmd_app_cmd = cmd[8];
  assign sdio_cmd_en = cmd[9];
  assign sdio_mmc_int_stop = cmd[11];
  assign sdio_bus_4bit = bwr[2];
  assign clr_rsp_crc_fail = clr[0];
  assign clr_dat_crc_fail = clr[1];
  assign clr_rsp_timeout = clr[2];
  assign clr_dat_timeout = clr[3];
  assign clr_rsp_crc_ok = clr[4];
  assign clr_dat_crc_ok = clr[5];
  assign clr_cmd_send = clr[6];
  assign clr_dat_end = clr[7];
  assign sdio_io_sdio_clkdiv = {1'b0,ccr[6 : 0]};
  assign sdio_io_sdio_dat_en = (dcr[6] && ($signed(32'h0) < $signed(dat_remaining)));
  assign sdio_io_sdio_dat_write = dcr[4];
  assign dma_en = dcr[5];
  assign one_value = 16'h0001;
  assign block_size = _zz_block_size[15 : 0];
  assign _zz_io_timeout_reset = clr[2];
  assign _zz_io_timeout_reset_2 = clr[3];
  assign sdio_io_timeout_reset = ((_zz_io_timeout_reset ^ _zz_io_timeout_reset_1) || (_zz_io_timeout_reset_2 ^ _zz_io_timeout_reset_3));
  assign dwr_read = (((apb_psel && apb_ptran) && (! apb_pwrite)) && (addr == 6'h10));
  assign dwr_writ = (((apb_psel && apb_ptran) && apb_pwrite) && (addr == 6'h10));
  assign recv_stream_data = {{{recv_stream_payload[7 : 0],recv_stream_payload[15 : 8]},recv_stream_payload[23 : 16]},recv_stream_payload[31 : 24]};
  assign send_stream_valid = dwr_writ;
  assign send_stream_payload = {{{_zz_send_stream_payload[7 : 0],_zz_send_stream_payload_1[15 : 8]},_zz_send_stream_payload_2[23 : 16]},_zz_send_stream_payload_3[31 : 24]};
  assign recv_stream_ready = (dwr_read && (! dwr_read_regNext));
  assign send_stream_ready = send_fifo_io_push_ready;
  assign recv_stream_valid = recv_fifo_io_pop_valid;
  assign recv_stream_payload = recv_fifo_io_pop_payload;
  assign recv_fifo_io_flush = dcr[10];
  assign send_fifo_io_flush = dcr[10];
  assign _zz_when_ftsdc010_l8 = clr[0];
  assign when_ftsdc010_l8 = (_zz_when_ftsdc010_l8 ^ _zz_when_ftsdc010_l8_1);
  assign when_ftsdc010_l10 = (sdio_io_crc_rsp_fail && (! toplevel_sdio_io_crc_rsp_fail_regNext));
  assign _zz_when_ftsdc010_l8_2 = clr[1];
  assign when_ftsdc010_l8_1 = (_zz_when_ftsdc010_l8_2 ^ _zz_when_ftsdc010_l8_3);
  assign when_ftsdc010_l10_1 = (sdio_io_crc_dat_fail && (! toplevel_sdio_io_crc_dat_fail_regNext));
  assign _zz_when_ftsdc010_l8_4 = clr[2];
  assign when_ftsdc010_l8_2 = (_zz_when_ftsdc010_l8_4 ^ _zz_when_ftsdc010_l8_5);
  assign when_ftsdc010_l10_2 = (sdio_io_timeout_rsp && (! toplevel_sdio_io_timeout_rsp_regNext));
  assign _zz_when_ftsdc010_l8_6 = clr[3];
  assign when_ftsdc010_l8_3 = (_zz_when_ftsdc010_l8_6 ^ _zz_when_ftsdc010_l8_7);
  assign when_ftsdc010_l10_3 = (sdio_io_timeout_dat && (! toplevel_sdio_io_timeout_dat_regNext));
  assign _zz_when_ftsdc010_l8_8 = clr[4];
  assign when_ftsdc010_l8_4 = (_zz_when_ftsdc010_l8_8 ^ _zz_when_ftsdc010_l8_9);
  assign when_ftsdc010_l10_4 = (sdio_io_crc_rsp_ok && (! toplevel_sdio_io_crc_rsp_ok_regNext));
  assign _zz_when_ftsdc010_l8_10 = clr[5];
  assign when_ftsdc010_l8_5 = (_zz_when_ftsdc010_l8_10 ^ _zz_when_ftsdc010_l8_11);
  assign when_ftsdc010_l10_5 = (sdio_io_crc_dat_ok && (! toplevel_sdio_io_crc_dat_ok_regNext));
  assign _zz_when_ftsdc010_l8_12 = clr[6];
  assign when_ftsdc010_l8_6 = (_zz_when_ftsdc010_l8_12 ^ _zz_when_ftsdc010_l8_13);
  assign when_ftsdc010_l10_6 = (sdio_io_cmd_send_done && (! toplevel_sdio_io_cmd_send_done_regNext));
  assign _zz_when_ftsdc010_l10 = (sdio_io_dat_end && ($signed(dat_remaining) <= $signed(32'h0)));
  assign _zz_when_ftsdc010_l8_14 = clr[7];
  assign when_ftsdc010_l8_7 = (_zz_when_ftsdc010_l8_14 ^ _zz_when_ftsdc010_l8_15);
  assign when_ftsdc010_l10_7 = (_zz_when_ftsdc010_l10 && (! _zz_when_ftsdc010_l10_1));
  always @(*) begin
    _zz_status_8 = 32'h0;
    _zz_status_8[0] = _zz_status;
    _zz_status_8[1] = _zz_status_1;
    _zz_status_8[2] = _zz_status_2;
    _zz_status_8[3] = _zz_status_3;
    _zz_status_8[4] = _zz_status_4;
    _zz_status_8[5] = _zz_status_5;
    _zz_status_8[6] = _zz_status_6;
    _zz_status_8[7] = _zz_status_7;
    _zz_status_8[9] = recv_stream_valid;
    _zz_status_8[8] = send_stream_ready;
    _zz_status_8[11] = 1'b1;
  end

  assign status = _zz_status_8;
  assign _zz_when_ftsdc010_l190 = cmd[10];
  assign when_ftsdc010_l190 = (_zz_when_ftsdc010_l190 && (! _zz_when_ftsdc010_l190_1));
  assign when_ftsdc010_l194 = (cmd[10] && (sdio_io_cmd_send_done && (! toplevel_sdio_io_cmd_send_done_regNext_1)));
  always @(*) begin
    cmd_ret[10] = (! sdc_rst);
    cmd_ret[31 : 11] = cmd[31 : 11];
    cmd_ret[9 : 0] = cmd[9 : 0];
  end

  always @(*) begin
    case(addr)
      6'h0 : begin
        read_data = cmd_ret;
      end
      6'h01 : begin
        read_data = argu;
      end
      6'h02 : begin
        read_data = sdio_io_sdio_rsp[39 : 8];
      end
      6'h03 : begin
        read_data = sdio_io_sdio_rsp[71 : 40];
      end
      6'h04 : begin
        read_data = sdio_io_sdio_rsp[103 : 72];
      end
      6'h05 : begin
        read_data = sdio_io_sdio_rsp[135 : 104];
      end
      6'h06 : begin
        read_data = rsp_cmd;
      end
      6'h07 : begin
        read_data = dcr;
      end
      6'h08 : begin
        read_data = dtr;
      end
      6'h09 : begin
        read_data = dat_remaining;
      end
      6'h0a : begin
        read_data = status;
      end
      6'h0b : begin
        read_data = clr;
      end
      6'h0c : begin
        read_data = int_mask;
      end
      6'h0d : begin
        read_data = pcr;
      end
      6'h0e : begin
        read_data = ccr;
      end
      6'h0f : begin
        read_data = bwr;
      end
      6'h10 : begin
        read_data = recv_stream_data;
      end
      6'h11 : begin
        read_data = feature;
      end
      6'h12 : begin
        read_data = rev;
      end
      6'h27 : begin
        read_data = feature;
      end
      6'h28 : begin
        read_data = rev;
      end
      default : begin
        read_data = 32'h0;
      end
    endcase
  end

  assign sdio_io_mmc_init = (sdio_sdc_rst ^ sdio_sdc_rst_regNext);
  assign when_ftsdc010_l240 = (cmd_en_trg ^ cmd_en_trg_regNext);
  assign when_ftsdc010_l245 = (dat_trg ^ dat_trg_regNext);
  assign when_ftsdc010_l252 = ($signed(_zz_when_ftsdc010_l252) < $signed(dat_remaining));
  assign when_ftsdc010_l258 = ($signed(dat_remaining) == $signed(_zz_when_ftsdc010_l258));
  assign when_ftsdc010_l249 = (sdio_io_dat_end && (! toplevel_sdio_io_dat_end_regNext));
  assign when_ftsdc010_l273 = (apb_psel && apb_ptran);
  assign when_ftsdc010_l275 = (! apb_pwrite);
  assign when_ftsdc010_l294 = apb_pwdata[10];
  assign when_ftsdc010_l316 = (apb_pwdata == 32'h0);
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      cmd <= 32'h0;
      argu <= 32'h0;
      rsp_cmd <= 32'h0;
      dcr <= 32'h0;
      dtr <= 32'h00989680;
      dlr <= 32'h0;
      clr <= 32'h0;
      int_mask <= 32'h0;
      pcr <= 32'h0;
      ccr <= 32'h0;
      bwr <= 32'h00000001;
      dwr <= 32'h0;
      prdata <= 32'h0;
      sdio_sdc_rst <= 1'b0;
      dat_remaining <= 32'h0;
      cmd_en_trg <= 1'b0;
      cmd_en <= 1'b0;
      send_valid <= 1'b0;
      send_payload <= 32'h0;
      _zz_status <= 1'b0;
      _zz_status_1 <= 1'b0;
      _zz_status_2 <= 1'b0;
      _zz_status_3 <= 1'b0;
      _zz_status_4 <= 1'b0;
      _zz_status_5 <= 1'b0;
      _zz_status_6 <= 1'b0;
      _zz_status_7 <= 1'b0;
      sdc_rst <= 1'b0;
      block_next <= 1'b0;
      dat_trg <= 1'b0;
    end else begin
      if(when_ftsdc010_l8) begin
        _zz_status <= 1'b0;
      end else begin
        if(when_ftsdc010_l10) begin
          _zz_status <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_1) begin
        _zz_status_1 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_1) begin
          _zz_status_1 <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_2) begin
        _zz_status_2 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_2) begin
          _zz_status_2 <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_3) begin
        _zz_status_3 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_3) begin
          _zz_status_3 <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_4) begin
        _zz_status_4 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_4) begin
          _zz_status_4 <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_5) begin
        _zz_status_5 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_5) begin
          _zz_status_5 <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_6) begin
        _zz_status_6 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_6) begin
          _zz_status_6 <= 1'b1;
        end
      end
      if(when_ftsdc010_l8_7) begin
        _zz_status_7 <= 1'b0;
      end else begin
        if(when_ftsdc010_l10_7) begin
          _zz_status_7 <= 1'b1;
        end
      end
      if(when_ftsdc010_l190) begin
        sdc_rst <= 1'b0;
      end else begin
        if(when_ftsdc010_l194) begin
          sdc_rst <= 1'b1;
        end
      end
      if(when_ftsdc010_l240) begin
        cmd_en <= 1'b1;
      end else begin
        if(when_ftsdc010_l245) begin
          dat_remaining <= dlr;
        end else begin
          if(when_ftsdc010_l249) begin
            if(when_ftsdc010_l252) begin
              block_next <= 1'b1;
              dat_remaining <= ($signed(dat_remaining) - $signed(_zz_dat_remaining));
            end else begin
              if(when_ftsdc010_l258) begin
                dat_remaining <= ($signed(dat_remaining) - $signed(_zz_dat_remaining_1));
              end
              block_next <= 1'b0;
            end
          end else begin
            block_next <= 1'b0;
          end
        end
        cmd_en <= 1'b0;
      end
      if(when_ftsdc010_l273) begin
        if(when_ftsdc010_l275) begin
          prdata <= read_data;
        end else begin
          case(addr)
            6'h0 : begin
              cmd <= apb_pwdata;
              sdio_sdc_rst <= (sdio_sdc_rst ^ apb_pwdata[10]);
              if(when_ftsdc010_l294) begin
                dcr <= 32'h00000009;
                ccr <= 32'h0;
                argu <= 32'h0;
              end
              cmd_en_trg <= (cmd_en_trg ^ apb_pwdata[9]);
            end
            6'h01 : begin
              argu <= apb_pwdata;
            end
            6'h06 : begin
              rsp_cmd <= apb_pwdata;
            end
            6'h07 : begin
              dcr <= apb_pwdata;
              dat_trg <= (dat_trg ^ apb_pwdata[6]);
            end
            6'h08 : begin
              if(when_ftsdc010_l316) begin
                dtr <= 32'h05f5e100;
              end else begin
                dtr <= apb_pwdata;
              end
            end
            6'h09 : begin
              dlr <= apb_pwdata;
            end
            6'h0b : begin
              clr <= (clr ^ apb_pwdata);
            end
            6'h0c : begin
              int_mask <= apb_pwdata;
            end
            6'h0d : begin
              pcr <= apb_pwdata;
            end
            6'h0e : begin
              ccr <= apb_pwdata;
            end
            6'h0f : begin
              bwr <= apb_pwdata;
            end
            6'h10 : begin
              dwr <= apb_pwdata;
              send_payload <= {{{_zz_send_payload[7 : 0],_zz_send_payload_1[15 : 8]},_zz_send_payload_2[23 : 16]},_zz_send_payload_3[31 : 24]};
              send_valid <= (! send_valid);
            end
            default : begin
            end
          endcase
        end
      end
    end
  end

  always @(posedge clk) begin
    _zz_io_timeout_reset_1 <= _zz_io_timeout_reset;
    _zz_io_timeout_reset_3 <= _zz_io_timeout_reset_2;
    dwr_read_regNext <= dwr_read;
    _zz_when_ftsdc010_l8_1 <= _zz_when_ftsdc010_l8;
    toplevel_sdio_io_crc_rsp_fail_regNext <= sdio_io_crc_rsp_fail;
    _zz_when_ftsdc010_l8_3 <= _zz_when_ftsdc010_l8_2;
    toplevel_sdio_io_crc_dat_fail_regNext <= sdio_io_crc_dat_fail;
    _zz_when_ftsdc010_l8_5 <= _zz_when_ftsdc010_l8_4;
    toplevel_sdio_io_timeout_rsp_regNext <= sdio_io_timeout_rsp;
    _zz_when_ftsdc010_l8_7 <= _zz_when_ftsdc010_l8_6;
    toplevel_sdio_io_timeout_dat_regNext <= sdio_io_timeout_dat;
    _zz_when_ftsdc010_l8_9 <= _zz_when_ftsdc010_l8_8;
    toplevel_sdio_io_crc_rsp_ok_regNext <= sdio_io_crc_rsp_ok;
    _zz_when_ftsdc010_l8_11 <= _zz_when_ftsdc010_l8_10;
    toplevel_sdio_io_crc_dat_ok_regNext <= sdio_io_crc_dat_ok;
    _zz_when_ftsdc010_l8_13 <= _zz_when_ftsdc010_l8_12;
    toplevel_sdio_io_cmd_send_done_regNext <= sdio_io_cmd_send_done;
    _zz_when_ftsdc010_l8_15 <= _zz_when_ftsdc010_l8_14;
    _zz_when_ftsdc010_l10_1 <= _zz_when_ftsdc010_l10;
    _zz_when_ftsdc010_l190_1 <= _zz_when_ftsdc010_l190;
    toplevel_sdio_io_cmd_send_done_regNext_1 <= sdio_io_cmd_send_done;
    sdio_sdc_rst_regNext <= sdio_sdc_rst;
    cmd_en_trg_regNext <= cmd_en_trg;
  end

  always @(posedge clk) begin
    dat_trg_regNext <= dat_trg;
    toplevel_sdio_io_dat_end_regNext <= sdio_io_dat_end;
  end


endmodule

//StreamFifo_1 replaced by StreamFifo

module StreamFifo (
  input  wire          io_push_valid,
  output wire          io_push_ready,
  input  wire [31:0]   io_push_payload,
  output wire          io_pop_valid,
  input  wire          io_pop_ready,
  output wire [31:0]   io_pop_payload,
  input  wire          io_flush,
  output wire [6:0]    io_occupancy,
  output wire [6:0]    io_availability,
  input  wire          clk,
  input  wire          reset
);

  reg        [31:0]   logic_ram_spinal_port1;
  reg                 _zz_1;
  wire                logic_ptr_doPush;
  wire                logic_ptr_doPop;
  wire                logic_ptr_full;
  wire                logic_ptr_empty;
  reg        [6:0]    logic_ptr_push;
  reg        [6:0]    logic_ptr_pop;
  wire       [6:0]    logic_ptr_occupancy;
  wire       [6:0]    logic_ptr_popOnIo;
  wire                when_Stream_l1248;
  reg                 logic_ptr_wentUp;
  wire                io_push_fire;
  wire                logic_push_onRam_write_valid;
  wire       [5:0]    logic_push_onRam_write_payload_address;
  wire       [31:0]   logic_push_onRam_write_payload_data;
  wire                logic_pop_addressGen_valid;
  reg                 logic_pop_addressGen_ready;
  wire       [5:0]    logic_pop_addressGen_payload;
  wire                logic_pop_addressGen_fire;
  wire                logic_pop_sync_readArbitation_valid;
  wire                logic_pop_sync_readArbitation_ready;
  wire       [5:0]    logic_pop_sync_readArbitation_payload;
  reg                 logic_pop_addressGen_rValid;
  reg        [5:0]    logic_pop_addressGen_rData;
  wire                when_Stream_l375;
  wire                logic_pop_sync_readPort_cmd_valid;
  wire       [5:0]    logic_pop_sync_readPort_cmd_payload;
  wire       [31:0]   logic_pop_sync_readPort_rsp;
  wire                logic_pop_sync_readArbitation_translated_valid;
  wire                logic_pop_sync_readArbitation_translated_ready;
  wire       [31:0]   logic_pop_sync_readArbitation_translated_payload;
  wire                logic_pop_sync_readArbitation_fire;
  reg        [6:0]    logic_pop_sync_popReg;
  reg [31:0] logic_ram [0:63];

  always @(posedge clk) begin
    if(_zz_1) begin
      logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data;
    end
  end

  always @(posedge clk) begin
    if(logic_pop_sync_readPort_cmd_valid) begin
      logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload];
    end
  end

  always @(*) begin
    _zz_1 = 1'b0;
    if(logic_push_onRam_write_valid) begin
      _zz_1 = 1'b1;
    end
  end

  assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop);
  assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 7'h40) == 7'h0);
  assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop);
  assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo);
  assign io_push_ready = (! logic_ptr_full);
  assign io_push_fire = (io_push_valid && io_push_ready);
  assign logic_ptr_doPush = io_push_fire;
  assign logic_push_onRam_write_valid = io_push_fire;
  assign logic_push_onRam_write_payload_address = logic_ptr_push[5:0];
  assign logic_push_onRam_write_payload_data = io_push_payload;
  assign logic_pop_addressGen_valid = (! logic_ptr_empty);
  assign logic_pop_addressGen_payload = logic_ptr_pop[5:0];
  assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready);
  assign logic_ptr_doPop = logic_pop_addressGen_fire;
  always @(*) begin
    logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready;
    if(when_Stream_l375) begin
      logic_pop_addressGen_ready = 1'b1;
    end
  end

  assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid);
  assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid;
  assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData;
  assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1;
  assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire;
  assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload;
  assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid;
  assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready;
  assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp;
  assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid;
  assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready;
  assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload;
  assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready);
  assign logic_ptr_popOnIo = logic_pop_sync_popReg;
  assign io_occupancy = logic_ptr_occupancy;
  assign io_availability = (7'h40 - logic_ptr_occupancy);
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      logic_ptr_push <= 7'h0;
      logic_ptr_pop <= 7'h0;
      logic_ptr_wentUp <= 1'b0;
      logic_pop_addressGen_rValid <= 1'b0;
      logic_pop_sync_popReg <= 7'h0;
    end else begin
      if(when_Stream_l1248) begin
        logic_ptr_wentUp <= logic_ptr_doPush;
      end
      if(io_flush) begin
        logic_ptr_wentUp <= 1'b0;
      end
      if(logic_ptr_doPush) begin
        logic_ptr_push <= (logic_ptr_push + 7'h01);
      end
      if(logic_ptr_doPop) begin
        logic_ptr_pop <= (logic_ptr_pop + 7'h01);
      end
      if(io_flush) begin
        logic_ptr_push <= 7'h0;
        logic_ptr_pop <= 7'h0;
      end
      if(logic_pop_addressGen_ready) begin
        logic_pop_addressGen_rValid <= logic_pop_addressGen_valid;
      end
      if(io_flush) begin
        logic_pop_addressGen_rValid <= 1'b0;
      end
      if(logic_pop_sync_readArbitation_fire) begin
        logic_pop_sync_popReg <= logic_ptr_pop;
      end
      if(io_flush) begin
        logic_pop_sync_popReg <= 7'h0;
      end
    end
  end

  always @(posedge clk) begin
    if(logic_pop_addressGen_ready) begin
      logic_pop_addressGen_rData <= logic_pop_addressGen_payload;
    end
  end


endmodule

module xsdio (
  output wire          io_sdio_clk,
  inout  wire [0:0]    io_sdio_cmd,
  inout  wire [3:0]    io_sdio_dat,
  input  wire          io_mmc_init,
  input  wire          io_sdio_cmd_en,
  input  wire [5:0]    io_sdio_cmd_valu,
  input  wire [31:0]   io_sdio_cmd_argu,
  input  wire          io_sdio_cmd_need_rsp,
  input  wire          io_sdio_cmd_long_rsp,
  output wire [255:0]  io_sdio_rsp,
  input  wire          io_sdio_bus_4bit,
  input  wire [7:0]    io_sdio_clkdiv,
  input  wire          io_dat_next_en,
  input  wire [15:0]   io_block_size,
  input  wire          io_sdio_dat_en,
  input  wire          io_sdio_dat_write,
  output wire          io_recv_stream_valid,
  input  wire          io_recv_stream_ready,
  output wire [31:0]   io_recv_stream_payload,
  input  wire          io_send_stream_valid,
  output wire          io_send_stream_ready,
  input  wire [31:0]   io_send_stream_payload,
  input  wire [31:0]   io_timeout_tick,
  input  wire          io_timeout_reset,
  output wire          io_busy,
  output wire          io_cmd_send_done,
  output wire          io_crc_rsp_ok,
  output wire          io_crc_dat_ok,
  output wire          io_crc_rsp_fail,
  output wire          io_crc_dat_fail,
  output wire          io_timeout,
  output wire          io_timeout_rsp,
  output wire          io_timeout_dat,
  output wire          io_dat_end,
  output wire          io_debug_flg,
  input  wire          clk,
  input  wire          reset
);

  wire       [5:0]    sdio_ctrl_1_io_cmd;
  wire       [31:0]   sdio_ctrl_1_io_argu;
  wire                sdio_ctrl_1_io_sdio_clk;
  wire                sdio_ctrl_1_io_cmd_done;
  wire                sdio_ctrl_1_io_cmd_busy;
  wire       [255:0]  sdio_ctrl_1_io_rsp;
  wire                sdio_ctrl_1_io_crc_rsp_ok;
  wire                sdio_ctrl_1_io_crc_rsp_fail;
  wire                sdio_ctrl_1_io_crc_dat_ok;
  wire                sdio_ctrl_1_io_crc_dat_fail;
  wire                sdio_ctrl_1_io_recv_stream_valid;
  wire       [31:0]   sdio_ctrl_1_io_recv_stream_payload;
  wire                sdio_ctrl_1_io_send_stream_ready;
  wire                sdio_ctrl_1_io_wait_rsp;
  wire                sdio_ctrl_1_io_wait_is_rsp;
  wire       [31:0]   _zz_io_timeout_1;
  wire       [31:0]   _zz_when_sdio_l883;
  reg        [31:0]   _zz_io_timeout;
  reg                 _zz_io_timeout_rsp;
  reg                 _zz_io_timeout_dat;
  reg                 _zz_io_dat_end;
  wire                _zz_when_sdio_l869;
  reg                 io_busy_regNext;
  wire                when_sdio_l865;
  reg                 _zz_when_sdio_l869_1;
  wire                when_sdio_l869;
  wire                when_sdio_l883;

  assign _zz_io_timeout_1 = io_timeout_tick;
  assign _zz_when_sdio_l883 = io_timeout_tick;
  sdio_ctrl sdio_ctrl_1 (
    .io_sdio_clk            (sdio_ctrl_1_io_sdio_clk                 ), //o
    .io_sdio_cmd            (io_sdio_cmd                             ), //~
    .io_sdio_dat            (io_sdio_dat                             ), //~
    .io_sdio_clkdiv         (io_sdio_clkdiv[7:0]                     ), //i
    .io_cmd_en              (io_sdio_cmd_en                          ), //i
    .io_cmd                 (sdio_ctrl_1_io_cmd[5:0]                 ), //i
    .io_cmd_done            (sdio_ctrl_1_io_cmd_done                 ), //o
    .io_argu                (sdio_ctrl_1_io_argu[31:0]               ), //i
    .io_cmd_busy            (sdio_ctrl_1_io_cmd_busy                 ), //o
    .io_need_rsp            (io_sdio_cmd_need_rsp                    ), //i
    .io_long_rsp            (io_sdio_cmd_long_rsp                    ), //i
    .io_bus_4bit            (io_sdio_bus_4bit                        ), //i
    .io_mmc_init            (io_mmc_init                             ), //i
    .io_rsp                 (sdio_ctrl_1_io_rsp[255:0]               ), //o
    .io_crc_rsp_ok          (sdio_ctrl_1_io_crc_rsp_ok               ), //o
    .io_crc_rsp_fail        (sdio_ctrl_1_io_crc_rsp_fail             ), //o
    .io_crc_dat_ok          (sdio_ctrl_1_io_crc_dat_ok               ), //o
    .io_crc_dat_fail        (sdio_ctrl_1_io_crc_dat_fail             ), //o
    .io_recv_stream_valid   (sdio_ctrl_1_io_recv_stream_valid        ), //o
    .io_recv_stream_ready   (io_recv_stream_ready                    ), //i
    .io_recv_stream_payload (sdio_ctrl_1_io_recv_stream_payload[31:0]), //o
    .io_send_stream_valid   (io_send_stream_valid                    ), //i
    .io_send_stream_ready   (sdio_ctrl_1_io_send_stream_ready        ), //o
    .io_send_stream_payload (io_send_stream_payload[31:0]            ), //i
    .io_block_size          (io_block_size[15:0]                     ), //i
    .io_wait_rsp            (sdio_ctrl_1_io_wait_rsp                 ), //o
    .io_wait_is_rsp         (sdio_ctrl_1_io_wait_is_rsp              ), //o
    .io_data_en             (io_sdio_dat_en                          ), //i
    .io_data_write          (io_sdio_dat_write                       ), //i
    .io_dat_next_en         (io_dat_next_en                          ), //i
    .clk                    (clk                                     ), //i
    .reset                  (reset                                   )  //i
  );
  assign io_debug_flg = 1'b0;
  assign io_sdio_clk = sdio_ctrl_1_io_sdio_clk;
  assign sdio_ctrl_1_io_cmd = io_sdio_cmd_valu;
  assign sdio_ctrl_1_io_argu = io_sdio_cmd_argu;
  assign io_recv_stream_payload = sdio_ctrl_1_io_recv_stream_payload;
  assign io_recv_stream_valid = sdio_ctrl_1_io_recv_stream_valid;
  assign io_send_stream_ready = sdio_ctrl_1_io_send_stream_ready;
  assign io_crc_rsp_ok = sdio_ctrl_1_io_crc_rsp_ok;
  assign io_crc_rsp_fail = sdio_ctrl_1_io_crc_rsp_fail;
  assign io_crc_dat_ok = sdio_ctrl_1_io_crc_dat_ok;
  assign io_crc_dat_fail = sdio_ctrl_1_io_crc_dat_fail;
  assign io_sdio_rsp = sdio_ctrl_1_io_rsp;
  assign io_cmd_send_done = sdio_ctrl_1_io_cmd_done;
  assign io_busy = sdio_ctrl_1_io_cmd_busy;
  assign io_timeout = ($signed(_zz_io_timeout_1) <= $signed(_zz_io_timeout));
  assign io_timeout_rsp = _zz_io_timeout_rsp;
  assign io_timeout_dat = _zz_io_timeout_dat;
  assign io_dat_end = _zz_io_dat_end;
  assign _zz_when_sdio_l869 = (sdio_ctrl_1_io_crc_dat_ok || sdio_ctrl_1_io_crc_dat_fail);
  assign when_sdio_l865 = (io_busy && (! io_busy_regNext));
  assign when_sdio_l869 = (_zz_when_sdio_l869 && (! _zz_when_sdio_l869_1));
  assign when_sdio_l883 = ($signed(_zz_io_timeout) < $signed(_zz_when_sdio_l883));
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      _zz_io_timeout <= 32'h0;
      _zz_io_timeout_rsp <= 1'b0;
      _zz_io_timeout_dat <= 1'b0;
      _zz_io_dat_end <= 1'b0;
    end else begin
      if(io_sdio_dat_en) begin
        if(when_sdio_l865) begin
          _zz_io_dat_end <= 1'b0;
        end else begin
          if(when_sdio_l869) begin
            _zz_io_dat_end <= 1'b1;
          end
        end
      end
      if(io_timeout_reset) begin
        _zz_io_timeout <= 32'h0;
      end else begin
        if(sdio_ctrl_1_io_wait_rsp) begin
          if(when_sdio_l883) begin
            _zz_io_timeout <= ($signed(_zz_io_timeout) + $signed(32'h00000001));
          end else begin
            _zz_io_timeout_rsp <= sdio_ctrl_1_io_wait_is_rsp;
            _zz_io_timeout_dat <= (! sdio_ctrl_1_io_wait_is_rsp);
          end
        end else begin
          _zz_io_timeout <= 32'h0;
          _zz_io_timeout_rsp <= 1'b0;
        end
      end
    end
  end

  always @(posedge clk) begin
    io_busy_regNext <= io_busy;
    _zz_when_sdio_l869_1 <= _zz_when_sdio_l869;
  end


endmodule

module sdio_ctrl (
  output wire          io_sdio_clk,
  inout  wire [0:0]    io_sdio_cmd,
  inout  wire [3:0]    io_sdio_dat,
  input  wire [7:0]    io_sdio_clkdiv,
  input  wire          io_cmd_en,
  input  wire [5:0]    io_cmd,
  output wire          io_cmd_done,
  input  wire [31:0]   io_argu,
  output wire          io_cmd_busy,
  input  wire          io_need_rsp,
  input  wire          io_long_rsp,
  input  wire          io_bus_4bit,
  input  wire          io_mmc_init,
  output wire [255:0]  io_rsp,
  output wire          io_crc_rsp_ok,
  output wire          io_crc_rsp_fail,
  output wire          io_crc_dat_ok,
  output wire          io_crc_dat_fail,
  output wire          io_recv_stream_valid,
  input  wire          io_recv_stream_ready,
  output wire [31:0]   io_recv_stream_payload,
  input  wire          io_send_stream_valid,
  output wire          io_send_stream_ready,
  input  wire [31:0]   io_send_stream_payload,
  input  wire [15:0]   io_block_size,
  output wire          io_wait_rsp,
  output wire          io_wait_is_rsp,
  input  wire          io_data_en,
  input  wire          io_data_write,
  input  wire          io_dat_next_en,
  input  wire          clk,
  input  wire          reset
);
  localparam fsm_enumDef_BOOT = 4'd0;
  localparam fsm_enumDef_idle = 4'd1;
  localparam fsm_enumDef_cmd_init = 4'd2;
  localparam fsm_enumDef_mmc_init = 4'd3;
  localparam fsm_enumDef_send_cmd = 4'd4;
  localparam fsm_enumDef_send_crc = 4'd5;
  localparam fsm_enumDef_rsp_recv = 4'd6;
  localparam fsm_enumDef_dat_recv_wait = 4'd7;
  localparam fsm_enumDef_dat_recv = 4'd8;
  localparam fsm_enumDef_dat_recv_crc = 4'd9;
  localparam fsm_enumDef_rsp_wait = 4'd10;
  localparam fsm_enumDef_dat_write = 4'd11;
  localparam fsm_enumDef_dat_write_crc = 4'd12;
  localparam fsm_enumDef_dat_write_rsp = 4'd13;
  localparam fsm_enumDef_dat_write_wait = 4'd14;

  wire                sdio_crc16_4_io_sdio_line;
  wire                sdio_crc16_5_io_sdio_line;
  wire                sdio_crc16_6_io_sdio_line;
  wire                sdio_crc16_7_io_sdio_line;
  wire       [7:0]    sdio_crc8_1_io_crc_out;
  wire       [15:0]   sdio_crc16_4_io_line_crc16;
  wire       [15:0]   sdio_crc16_5_io_line_crc16;
  wire       [15:0]   sdio_crc16_6_io_line_crc16;
  wire       [15:0]   sdio_crc16_7_io_line_crc16;
  wire       [15:0]   _zz_crc16_p0_1;
  wire       [16:0]   _zz_crc16_p0_2;
  wire       [15:0]   _zz_crc16_p1_1;
  wire       [16:0]   _zz_crc16_p1_2;
  wire       [15:0]   _zz_crc16_p2_1;
  wire       [16:0]   _zz_crc16_p2_2;
  wire       [15:0]   _zz_crc16_p3_1;
  wire       [16:0]   _zz_crc16_p3_2;
  wire       [0:0]    _zz_io_sdio_cmd_1;
  reg                 _zz_io_sdio_dat;
  reg                 _zz_io_sdio_cmd;
  reg        [7:0]    clk_cnt;
  wire                when_sdio_l286;
  reg        [3:0]    dat_o;
  reg                 dat_oe;
  reg                 cmd_o;
  reg                 cmd_oe;
  reg                 sdio_clk;
  wire                clk_edge;
  wire                clk_lo;
  reg        [7:0]    dat_rsp;
  reg                 cmd_done;
  wire       [39:0]   cmd_seq;
  reg        [39:0]   cmd_dat;
  reg        [7:0]    cmd_remaining;
  reg        [7:0]    wait_remaining;
  reg        [8:0]    rsp_remaining;
  reg                 _zz_io_calc_en;
  reg                 _zz_io_crc_reset;
  wire       [7:0]    _zz_cmd_dat;
  reg        [255:0]  rsp;
  reg        [7:0]    rsp_crc;
  reg                 crc_rsp_ok;
  reg                 crc_rsp_fail;
  reg        [15:0]   block_remaining;
  reg        [7:0]    send_remaining;
  reg                 _zz_io_line_reset;
  reg                 _zz_io_calc_en_1;
  wire       [15:0]   _zz_crc0;
  wire       [15:0]   _zz_crc1;
  wire       [15:0]   _zz_crc2;
  wire       [15:0]   _zz_crc3;
  reg                 debug_flg;
  reg        [15:0]   crc0;
  reg        [15:0]   crc1;
  reg        [15:0]   crc2;
  reg        [15:0]   crc3;
  reg        [15:0]   recv0;
  reg        [15:0]   recv1;
  reg        [15:0]   recv2;
  reg        [15:0]   recv3;
  reg        [15:0]   crc16_p0;
  wire       [15:0]   _zz_crc16_p0;
  reg        [15:0]   crc16_p1;
  wire       [15:0]   _zz_crc16_p1;
  reg        [15:0]   crc16_p2;
  wire       [15:0]   _zz_crc16_p2;
  reg        [15:0]   crc16_p3;
  wire       [15:0]   _zz_crc16_p3;
  reg        [31:0]   send_payload;
  reg                 send_payload_trg;
  reg                 send_payload_trg_regNext;
  reg                 crc_dat_ok;
  reg                 crc_dat_fail;
  wire                fsm_wantExit;
  reg                 fsm_wantStart;
  wire                fsm_wantKill;
  reg        [32:0]   recv_stream_payload;
  wire                _zz_io_recv_stream_valid;
  reg                 _zz_io_recv_stream_valid_1;
  reg        [3:0]    fsm_stateReg;
  reg        [3:0]    fsm_stateNext;
  reg                 io_mmc_init_regNext;
  wire                when_sdio_l376;
  wire                when_sdio_l386;
  reg                 io_cmd_en_regNext;
  wire                when_sdio_l381;
  reg                 io_dat_next_en_regNext;
  wire                when_sdio_l385;
  wire                when_sdio_l412;
  wire                when_sdio_l427;
  wire                when_sdio_l446;
  wire                when_sdio_l452;
  wire                when_sdio_l475;
  wire                when_sdio_l478;
  wire                when_sdio_l496;
  wire                when_sdio_l511;
  wire                when_sdio_l486;
  wire                when_sdio_l492;
  wire                when_sdio_l527;
  wire                when_sdio_l546;
  wire                when_sdio_l547;
  wire                when_sdio_l559;
  wire                when_sdio_l574;
  wire                when_sdio_l583;
  wire                when_sdio_l578;
  wire                when_sdio_l605;
  wire                when_sdio_l619;
  wire                when_sdio_l633;
  wire                when_sdio_l649;
  wire                when_sdio_l653;
  wire                when_sdio_l678;
  wire                when_sdio_l683;
  wire                when_sdio_l691;
  wire                when_sdio_l696;
  reg                 io_mmc_init_regNext_1;
  wire                when_sdio_l365;
  `ifndef SYNTHESIS
  reg [111:0] fsm_stateReg_string;
  reg [111:0] fsm_stateNext_string;
  `endif


  assign _zz_crc16_p0_1 = (_zz_crc16_p0_2[15 : 0] ^ (crc16_p0[15] ? _zz_crc16_p0 : 16'h0));
  assign _zz_crc16_p0_2 = {crc16_p0,1'b0};
  assign _zz_crc16_p1_1 = (_zz_crc16_p1_2[15 : 0] ^ (crc16_p1[15] ? _zz_crc16_p1 : 16'h0));
  assign _zz_crc16_p1_2 = {crc16_p1,1'b0};
  assign _zz_crc16_p2_1 = (_zz_crc16_p2_2[15 : 0] ^ (crc16_p2[15] ? _zz_crc16_p2 : 16'h0));
  assign _zz_crc16_p2_2 = {crc16_p2,1'b0};
  assign _zz_crc16_p3_1 = (_zz_crc16_p3_2[15 : 0] ^ (crc16_p3[15] ? _zz_crc16_p3 : 16'h0));
  assign _zz_crc16_p3_2 = {crc16_p3,1'b0};
  assign _zz_io_sdio_cmd_1 = cmd_o;
  sdio_crc8 sdio_crc8_1 (
    .io_sdio_clk  (io_sdio_clk                ), //i
    .io_sdio_line (io_sdio_cmd                ), //i
    .io_calc_en   (_zz_io_calc_en             ), //i
    .io_crc_reset (_zz_io_crc_reset           ), //i
    .io_crc_out   (sdio_crc8_1_io_crc_out[7:0]), //o
    .io_crc_in    (sdio_crc8_1_io_crc_out[7:0]), //i
    .clk          (clk                        ), //i
    .reset        (reset                      )  //i
  );
  sdio_crc16 sdio_crc16_4 (
    .io_sdio_clk   (io_sdio_clk                     ), //i
    .io_sdio_line  (sdio_crc16_4_io_sdio_line       ), //i
    .io_calc_en    (_zz_io_calc_en_1                ), //i
    .io_line_reset (_zz_io_line_reset               ), //i
    .io_line_crc16 (sdio_crc16_4_io_line_crc16[15:0]), //o
    .clk           (clk                             ), //i
    .reset         (reset                           )  //i
  );
  sdio_crc16 sdio_crc16_5 (
    .io_sdio_clk   (io_sdio_clk                     ), //i
    .io_sdio_line  (sdio_crc16_5_io_sdio_line       ), //i
    .io_calc_en    (_zz_io_calc_en_1                ), //i
    .io_line_reset (_zz_io_line_reset               ), //i
    .io_line_crc16 (sdio_crc16_5_io_line_crc16[15:0]), //o
    .clk           (clk                             ), //i
    .reset         (reset                           )  //i
  );
  sdio_crc16 sdio_crc16_6 (
    .io_sdio_clk   (io_sdio_clk                     ), //i
    .io_sdio_line  (sdio_crc16_6_io_sdio_line       ), //i
    .io_calc_en    (_zz_io_calc_en_1                ), //i
    .io_line_reset (_zz_io_line_reset               ), //i
    .io_line_crc16 (sdio_crc16_6_io_line_crc16[15:0]), //o
    .clk           (clk                             ), //i
    .reset         (reset                           )  //i
  );
  sdio_crc16 sdio_crc16_7 (
    .io_sdio_clk   (io_sdio_clk                     ), //i
    .io_sdio_line  (sdio_crc16_7_io_sdio_line       ), //i
    .io_calc_en    (_zz_io_calc_en_1                ), //i
    .io_line_reset (_zz_io_line_reset               ), //i
    .io_line_crc16 (sdio_crc16_7_io_line_crc16[15:0]), //o
    .clk           (clk                             ), //i
    .reset         (reset                           )  //i
  );
  assign io_sdio_cmd = _zz_io_sdio_cmd ? _zz_io_sdio_cmd_1[0 : 0] : 1'bz;
  assign io_sdio_dat = _zz_io_sdio_dat ? dat_o[3 : 0] : 4'bzzzz;
  `ifndef SYNTHESIS
  always @(*) begin
    case(fsm_stateReg)
      fsm_enumDef_BOOT : fsm_stateReg_string = "BOOT          ";
      fsm_enumDef_idle : fsm_stateReg_string = "idle          ";
      fsm_enumDef_cmd_init : fsm_stateReg_string = "cmd_init      ";
      fsm_enumDef_mmc_init : fsm_stateReg_string = "mmc_init      ";
      fsm_enumDef_send_cmd : fsm_stateReg_string = "send_cmd      ";
      fsm_enumDef_send_crc : fsm_stateReg_string = "send_crc      ";
      fsm_enumDef_rsp_recv : fsm_stateReg_string = "rsp_recv      ";
      fsm_enumDef_dat_recv_wait : fsm_stateReg_string = "dat_recv_wait ";
      fsm_enumDef_dat_recv : fsm_stateReg_string = "dat_recv      ";
      fsm_enumDef_dat_recv_crc : fsm_stateReg_string = "dat_recv_crc  ";
      fsm_enumDef_rsp_wait : fsm_stateReg_string = "rsp_wait      ";
      fsm_enumDef_dat_write : fsm_stateReg_string = "dat_write     ";
      fsm_enumDef_dat_write_crc : fsm_stateReg_string = "dat_write_crc ";
      fsm_enumDef_dat_write_rsp : fsm_stateReg_string = "dat_write_rsp ";
      fsm_enumDef_dat_write_wait : fsm_stateReg_string = "dat_write_wait";
      default : fsm_stateReg_string = "??????????????";
    endcase
  end
  always @(*) begin
    case(fsm_stateNext)
      fsm_enumDef_BOOT : fsm_stateNext_string = "BOOT          ";
      fsm_enumDef_idle : fsm_stateNext_string = "idle          ";
      fsm_enumDef_cmd_init : fsm_stateNext_string = "cmd_init      ";
      fsm_enumDef_mmc_init : fsm_stateNext_string = "mmc_init      ";
      fsm_enumDef_send_cmd : fsm_stateNext_string = "send_cmd      ";
      fsm_enumDef_send_crc : fsm_stateNext_string = "send_crc      ";
      fsm_enumDef_rsp_recv : fsm_stateNext_string = "rsp_recv      ";
      fsm_enumDef_dat_recv_wait : fsm_stateNext_string = "dat_recv_wait ";
      fsm_enumDef_dat_recv : fsm_stateNext_string = "dat_recv      ";
      fsm_enumDef_dat_recv_crc : fsm_stateNext_string = "dat_recv_crc  ";
      fsm_enumDef_rsp_wait : fsm_stateNext_string = "rsp_wait      ";
      fsm_enumDef_dat_write : fsm_stateNext_string = "dat_write     ";
      fsm_enumDef_dat_write_crc : fsm_stateNext_string = "dat_write_crc ";
      fsm_enumDef_dat_write_rsp : fsm_stateNext_string = "dat_write_rsp ";
      fsm_enumDef_dat_write_wait : fsm_stateNext_string = "dat_write_wait";
      default : fsm_stateNext_string = "??????????????";
    endcase
  end
  `endif

  always @(*) begin
    _zz_io_sdio_dat = 1'b0;
    if(dat_oe) begin
      _zz_io_sdio_dat = 1'b1;
    end
  end

  always @(*) begin
    _zz_io_sdio_cmd = 1'b0;
    if(cmd_oe) begin
      _zz_io_sdio_cmd = 1'b1;
    end
  end

  assign when_sdio_l286 = ($signed(clk_cnt) < $signed(io_sdio_clkdiv));
  assign clk_edge = ($signed(clk_cnt) == $signed(io_sdio_clkdiv));
  assign clk_lo = (! sdio_clk);
  assign io_sdio_clk = sdio_clk;
  assign cmd_seq = {{2'b01,io_cmd},io_argu[31 : 0]};
  assign _zz_cmd_dat = sdio_crc8_1_io_crc_out;
  assign io_rsp = rsp;
  assign io_cmd_done = cmd_done;
  assign io_crc_rsp_ok = crc_rsp_ok;
  assign io_crc_rsp_fail = crc_rsp_fail;
  assign sdio_crc16_4_io_sdio_line = io_sdio_dat[0];
  assign _zz_crc0 = sdio_crc16_4_io_line_crc16;
  assign sdio_crc16_5_io_sdio_line = io_sdio_dat[1];
  assign _zz_crc1 = sdio_crc16_5_io_line_crc16;
  assign sdio_crc16_6_io_sdio_line = io_sdio_dat[2];
  assign _zz_crc2 = sdio_crc16_6_io_line_crc16;
  assign sdio_crc16_7_io_sdio_line = io_sdio_dat[3];
  assign _zz_crc3 = sdio_crc16_7_io_line_crc16;
  assign _zz_crc16_p0 = 16'h1021;
  assign _zz_crc16_p1 = 16'h1021;
  assign _zz_crc16_p2 = 16'h1021;
  assign _zz_crc16_p3 = 16'h1021;
  assign io_send_stream_ready = (send_payload_trg ^ send_payload_trg_regNext);
  assign io_crc_dat_ok = crc_dat_ok;
  assign io_crc_dat_fail = crc_dat_fail;
  assign fsm_wantExit = 1'b0;
  always @(*) begin
    fsm_wantStart = 1'b0;
    case(fsm_stateReg)
      fsm_enumDef_idle : begin
      end
      fsm_enumDef_cmd_init : begin
      end
      fsm_enumDef_mmc_init : begin
      end
      fsm_enumDef_send_cmd : begin
      end
      fsm_enumDef_send_crc : begin
      end
      fsm_enumDef_rsp_recv : begin
      end
      fsm_enumDef_dat_recv_wait : begin
      end
      fsm_enumDef_dat_recv : begin
      end
      fsm_enumDef_dat_recv_crc : begin
      end
      fsm_enumDef_rsp_wait : begin
      end
      fsm_enumDef_dat_write : begin
      end
      fsm_enumDef_dat_write_crc : begin
      end
      fsm_enumDef_dat_write_rsp : begin
      end
      fsm_enumDef_dat_write_wait : begin
      end
      default : begin
        fsm_wantStart = 1'b1;
      end
    endcase
  end

  assign fsm_wantKill = 1'b0;
  assign io_recv_stream_payload = recv_stream_payload[31 : 0];
  assign _zz_io_recv_stream_valid = recv_stream_payload[32];
  assign io_recv_stream_valid = ((_zz_io_recv_stream_valid && (! _zz_io_recv_stream_valid_1)) && (fsm_stateReg == fsm_enumDef_dat_recv));
  assign io_wait_rsp = (((fsm_stateReg == fsm_enumDef_dat_recv_wait) || (fsm_stateReg == fsm_enumDef_rsp_wait)) || (fsm_stateReg == fsm_enumDef_dat_write_rsp));
  assign io_wait_is_rsp = (fsm_stateReg == fsm_enumDef_rsp_wait);
  assign io_cmd_busy = (! (fsm_stateReg == fsm_enumDef_idle));
  always @(*) begin
    fsm_stateNext = fsm_stateReg;
    case(fsm_stateReg)
      fsm_enumDef_idle : begin
        if(when_sdio_l376) begin
          fsm_stateNext = fsm_enumDef_mmc_init;
        end else begin
          if(when_sdio_l381) begin
            fsm_stateNext = fsm_enumDef_cmd_init;
          end else begin
            if(when_sdio_l385) begin
              if(when_sdio_l386) begin
                fsm_stateNext = fsm_enumDef_dat_recv_wait;
              end
            end else begin
              if(io_send_stream_valid) begin
                fsm_stateNext = fsm_enumDef_dat_write_wait;
              end
            end
          end
        end
      end
      fsm_enumDef_cmd_init : begin
        fsm_stateNext = fsm_enumDef_send_cmd;
      end
      fsm_enumDef_mmc_init : begin
        if(!when_sdio_l412) begin
          fsm_stateNext = fsm_enumDef_idle;
        end
      end
      fsm_enumDef_send_cmd : begin
        if(!when_sdio_l427) begin
          fsm_stateNext = fsm_enumDef_send_crc;
        end
      end
      fsm_enumDef_send_crc : begin
        if(!when_sdio_l446) begin
          if(!when_sdio_l452) begin
            if(io_need_rsp) begin
              fsm_stateNext = fsm_enumDef_rsp_wait;
            end else begin
              fsm_stateNext = fsm_enumDef_idle;
            end
          end
        end
      end
      fsm_enumDef_rsp_recv : begin
        if(!when_sdio_l478) begin
          if(!when_sdio_l486) begin
            if(!when_sdio_l492) begin
              if(when_sdio_l511) begin
                fsm_stateNext = fsm_enumDef_dat_recv_wait;
              end else begin
                fsm_stateNext = fsm_enumDef_idle;
              end
            end
          end
        end
      end
      fsm_enumDef_dat_recv_wait : begin
        if(sdio_clk) begin
          if(clk_edge) begin
            if(when_sdio_l527) begin
              fsm_stateNext = fsm_enumDef_dat_recv;
            end
          end
        end
      end
      fsm_enumDef_dat_recv : begin
        if(!when_sdio_l546) begin
          fsm_stateNext = fsm_enumDef_dat_recv_crc;
        end
      end
      fsm_enumDef_dat_recv_crc : begin
        if(!when_sdio_l574) begin
          if(!when_sdio_l578) begin
            fsm_stateNext = fsm_enumDef_idle;
          end
        end
      end
      fsm_enumDef_rsp_wait : begin
        if(clk_lo) begin
          if(clk_edge) begin
            if(when_sdio_l605) begin
              fsm_stateNext = fsm_enumDef_rsp_recv;
            end
          end
        end
      end
      fsm_enumDef_dat_write : begin
        if(!when_sdio_l619) begin
          if(when_sdio_l633) begin
            fsm_stateNext = fsm_enumDef_dat_write_crc;
          end
        end
      end
      fsm_enumDef_dat_write_crc : begin
        if(!when_sdio_l649) begin
          if(!when_sdio_l653) begin
            fsm_stateNext = fsm_enumDef_dat_write_rsp;
          end
        end
      end
      fsm_enumDef_dat_write_rsp : begin
        if(when_sdio_l678) begin
          if(when_sdio_l683) begin
            fsm_stateNext = fsm_enumDef_idle;
          end
        end
      end
      fsm_enumDef_dat_write_wait : begin
        if(clk_lo) begin
          if(clk_edge) begin
            fsm_stateNext = fsm_enumDef_dat_write;
          end
        end
      end
      default : begin
      end
    endcase
    if(when_sdio_l365) begin
      fsm_stateNext = fsm_enumDef_mmc_init;
    end
    if(fsm_wantStart) begin
      fsm_stateNext = fsm_enumDef_idle;
    end
    if(fsm_wantKill) begin
      fsm_stateNext = fsm_enumDef_BOOT;
    end
  end

  assign when_sdio_l376 = (io_mmc_init && (! io_mmc_init_regNext));
  assign when_sdio_l386 = (! io_data_write);
  assign when_sdio_l381 = (io_cmd_en && (! io_cmd_en_regNext));
  assign when_sdio_l385 = (io_dat_next_en && (! io_dat_next_en_regNext));
  assign when_sdio_l412 = ($signed(8'h0) <= $signed(wait_remaining));
  assign when_sdio_l427 = ($signed(8'h0) <= $signed(cmd_remaining));
  assign when_sdio_l446 = ($signed(8'h0) < $signed(wait_remaining));
  assign when_sdio_l452 = (! cmd_dat[20]);
  assign when_sdio_l475 = ($signed(rsp_remaining) == $signed(9'h081));
  assign when_sdio_l478 = ($signed(9'h009) < $signed(rsp_remaining));
  assign when_sdio_l496 = ($signed(9'h001) < $signed(rsp_remaining));
  assign when_sdio_l511 = (io_data_en && (! io_data_write));
  assign when_sdio_l486 = ($signed(8'h0) <= $signed(wait_remaining));
  assign when_sdio_l492 = ($signed(9'h0) <= $signed(rsp_remaining));
  assign when_sdio_l527 = (! io_sdio_dat[0]);
  assign when_sdio_l546 = ($signed(16'h0) <= $signed(block_remaining));
  assign when_sdio_l547 = (! recv_stream_payload[32]);
  assign when_sdio_l559 = ((! io_recv_stream_valid) && io_recv_stream_ready);
  assign when_sdio_l574 = ($signed(8'h11) < $signed(wait_remaining));
  assign when_sdio_l583 = ($signed(8'h0) < $signed(wait_remaining));
  assign when_sdio_l578 = ($signed(8'h0) <= $signed(wait_remaining));
  assign when_sdio_l605 = (io_sdio_cmd == 1'b0);
  assign when_sdio_l619 = ($signed(8'h0) <= $signed(send_remaining));
  assign when_sdio_l633 = ($signed(block_remaining) <= $signed(16'h0));
  assign when_sdio_l649 = ($signed(8'h10) < $signed(wait_remaining));
  assign when_sdio_l653 = ($signed(8'h0) <= $signed(wait_remaining));
  assign when_sdio_l678 = ($signed(8'h0) < $signed(wait_remaining));
  assign when_sdio_l683 = ($signed(wait_remaining) == $signed(8'h01));
  assign when_sdio_l691 = (dat_rsp[7] != 1'b0);
  assign when_sdio_l696 = io_sdio_dat[0];
  assign when_sdio_l365 = (io_mmc_init && (! io_mmc_init_regNext_1));
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      clk_cnt <= 8'h0;
      dat_o <= 4'b0000;
      dat_oe <= 1'b0;
      cmd_o <= 1'b1;
      cmd_oe <= 1'b0;
      sdio_clk <= 1'b1;
      dat_rsp <= 8'h0;
      cmd_done <= 1'b0;
      cmd_dat <= 40'h0;
      cmd_remaining <= 8'h0;
      wait_remaining <= 8'h0;
      rsp_remaining <= 9'h0;
      _zz_io_calc_en <= 1'b0;
      _zz_io_crc_reset <= 1'b0;
      rsp <= 256'h0;
      rsp_crc <= 8'h0;
      crc_rsp_ok <= 1'b0;
      crc_rsp_fail <= 1'b0;
      block_remaining <= 16'h0;
      send_remaining <= 8'h0;
      _zz_io_line_reset <= 1'b0;
      _zz_io_calc_en_1 <= 1'b0;
      debug_flg <= 1'b0;
      crc0 <= 16'h0;
      crc1 <= 16'h0;
      crc2 <= 16'h0;
      crc3 <= 16'h0;
      recv0 <= 16'h0;
      recv1 <= 16'h0;
      recv2 <= 16'h0;
      recv3 <= 16'h0;
      crc16_p0 <= 16'h0;
      crc16_p1 <= 16'h0;
      crc16_p2 <= 16'h0;
      crc16_p3 <= 16'h0;
      send_payload <= 32'h0;
      send_payload_trg <= 1'b0;
      crc_dat_ok <= 1'b0;
      crc_dat_fail <= 1'b0;
      recv_stream_payload <= 33'h0;
      fsm_stateReg <= fsm_enumDef_BOOT;
    end else begin
      if(when_sdio_l286) begin
        clk_cnt <= ($signed(clk_cnt) + $signed(8'h01));
      end else begin
        clk_cnt <= 8'h0;
      end
      fsm_stateReg <= fsm_stateNext;
      case(fsm_stateReg)
        fsm_enumDef_idle : begin
          if(clk_lo) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
            end
          end
          cmd_oe <= 1'b0;
          dat_oe <= 1'b0;
          if(when_sdio_l376) begin
            wait_remaining <= 8'h7f;
            cmd_done <= 1'b0;
          end else begin
            if(when_sdio_l381) begin
              cmd_done <= 1'b0;
            end else begin
              if(!when_sdio_l385) begin
                if(io_send_stream_valid) begin
                  _zz_io_line_reset <= 1'b1;
                end
              end
            end
          end
        end
        fsm_enumDef_cmd_init : begin
          cmd_remaining <= 8'h28;
          _zz_io_crc_reset <= 1'b1;
          _zz_io_calc_en <= 1'b1;
          cmd_oe <= 1'b1;
          cmd_dat <= cmd_seq;
        end
        fsm_enumDef_mmc_init : begin
          if(when_sdio_l412) begin
            if(sdio_clk) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
              end
            end
            if(clk_lo) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
              end
            end
          end else begin
            cmd_done <= 1'b1;
          end
        end
        fsm_enumDef_send_cmd : begin
          if(when_sdio_l427) begin
            _zz_io_crc_reset <= 1'b0;
            _zz_io_calc_en <= 1'b1;
            if(sdio_clk) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                cmd_remaining <= ($signed(cmd_remaining) - $signed(8'h01));
                cmd_o <= cmd_dat[39];
                cmd_dat <= {cmd_dat[38 : 0],1'b1};
              end
            end
            if(clk_lo) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
              end
            end
          end else begin
            wait_remaining <= 8'h06;
          end
        end
        fsm_enumDef_send_crc : begin
          if(when_sdio_l446) begin
            wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
            cmd_dat[7 : 0] <= {_zz_cmd_dat[6 : 0],1'b1};
            cmd_dat[39 : 8] <= 32'h00000001;
          end else begin
            if(when_sdio_l452) begin
              cmd_o <= cmd_dat[7];
              if(sdio_clk) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                  cmd_dat <= {cmd_dat[38 : 0],1'b1};
                end
              end
              if(clk_lo) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                end
              end
            end else begin
              if(!io_need_rsp) begin
                cmd_done <= 1'b1;
              end
            end
          end
        end
        fsm_enumDef_rsp_recv : begin
          if(when_sdio_l475) begin
            _zz_io_calc_en <= 1'b1;
          end
          if(when_sdio_l478) begin
            wait_remaining <= 8'h04;
            if(clk_lo) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
              end
            end
            if(sdio_clk) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                rsp_remaining <= ($signed(rsp_remaining) - $signed(9'h001));
                rsp <= {rsp[254 : 0],io_sdio_cmd};
              end
            end
          end else begin
            if(when_sdio_l486) begin
              rsp_crc <= _zz_cmd_dat;
              _zz_io_calc_en <= 1'b0;
              wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
            end else begin
              if(when_sdio_l492) begin
                if(sdio_clk) begin
                  if(clk_edge) begin
                    sdio_clk <= (! sdio_clk);
                    rsp_remaining <= ($signed(rsp_remaining) - $signed(9'h001));
                    if(when_sdio_l496) begin
                      rsp <= {rsp[254 : 0],io_sdio_cmd};
                    end
                  end
                end
                if(clk_lo) begin
                  if(clk_edge) begin
                    sdio_clk <= (! sdio_clk);
                  end
                end
              end else begin
                crc_rsp_ok <= ((rsp[7 : 1] == rsp_crc[6 : 0]) || (rsp[7 : 0] == 8'hff));
                crc_rsp_fail <= ((rsp[7 : 1] != rsp_crc[6 : 0]) && (rsp[7 : 0] != 8'hff));
                if(io_long_rsp) begin
                  rsp <= {rsp[247 : 0],8'h0};
                end
                cmd_done <= 1'b1;
              end
            end
          end
        end
        fsm_enumDef_dat_recv_wait : begin
          recv_stream_payload <= (~ 33'h0);
          block_remaining <= ($signed(io_block_size) >>> 2);
          if(sdio_clk) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
              if(when_sdio_l527) begin
                crc16_p0 <= 16'h0;
                crc16_p1 <= 16'h0;
                crc16_p2 <= 16'h0;
                crc16_p3 <= 16'h0;
                _zz_io_line_reset <= 1'b0;
                _zz_io_calc_en_1 <= 1'b1;
              end else begin
                crc_dat_ok <= 1'b0;
                crc_dat_fail <= 1'b0;
                _zz_io_calc_en_1 <= 1'b1;
                _zz_io_line_reset <= 1'b1;
              end
            end
          end
          if(clk_lo) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
            end
          end
        end
        fsm_enumDef_dat_recv : begin
          if(when_sdio_l546) begin
            if(when_sdio_l547) begin
              if(sdio_clk) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                  crc16_p0 <= (_zz_crc16_p0_1[15 : 0] ^ (io_sdio_dat[0] ? _zz_crc16_p0 : 16'h0));
                  crc16_p1 <= (_zz_crc16_p1_1[15 : 0] ^ (io_sdio_dat[1] ? _zz_crc16_p1 : 16'h0));
                  crc16_p2 <= (_zz_crc16_p2_1[15 : 0] ^ (io_sdio_dat[2] ? _zz_crc16_p2 : 16'h0));
                  crc16_p3 <= (_zz_crc16_p3_1[15 : 0] ^ (io_sdio_dat[3] ? _zz_crc16_p3 : 16'h0));
                  if(io_bus_4bit) begin
                    recv_stream_payload <= {recv_stream_payload[28 : 0],io_sdio_dat};
                  end else begin
                    recv_stream_payload <= {recv_stream_payload[31 : 0],io_sdio_dat[0]};
                  end
                end
              end
              if(clk_lo) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                end
              end
            end else begin
              if(when_sdio_l559) begin
                block_remaining <= ($signed(block_remaining) - $signed(16'h0001));
                recv_stream_payload <= 33'h000000001;
              end
            end
          end else begin
            wait_remaining <= 8'h14;
          end
        end
        fsm_enumDef_dat_recv_crc : begin
          if(when_sdio_l574) begin
            wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
            crc0 <= _zz_crc0;
            crc1 <= _zz_crc1;
            crc2 <= _zz_crc2;
            crc3 <= _zz_crc3;
            debug_flg <= 1'b1;
          end else begin
            if(when_sdio_l578) begin
              if(sdio_clk) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                  wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
                end
              end
              if(clk_lo) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                  if(when_sdio_l583) begin
                    recv0 <= {recv0[14 : 0],io_sdio_dat[0]};
                    recv1 <= {recv1[14 : 0],io_sdio_dat[1]};
                    recv2 <= {recv2[14 : 0],io_sdio_dat[2]};
                    recv3 <= {recv3[14 : 0],io_sdio_dat[3]};
                    debug_flg <= 1'b0;
                  end
                end
              end
            end else begin
              crc_dat_ok <= (io_bus_4bit ? ((((crc16_p0 == recv0) && (crc16_p1 == recv1)) && (crc16_p2 == recv2)) && (crc16_p3 == recv3)) : (crc16_p0 == recv0));
              crc_dat_fail <= (io_bus_4bit ? ((((crc16_p0 != recv0) || (crc16_p1 != recv1)) || (crc16_p2 != recv2)) || (crc16_p3 != recv3)) : (crc16_p0 != recv0));
            end
          end
        end
        fsm_enumDef_rsp_wait : begin
          _zz_io_calc_en <= (! io_long_rsp);
          crc_rsp_ok <= 1'b0;
          crc_rsp_fail <= 1'b0;
          cmd_oe <= 1'b0;
          rsp <= 256'h0;
          rsp_remaining <= (io_long_rsp ? 9'h088 : 9'h030);
          if(clk_lo) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
              if(when_sdio_l605) begin
                _zz_io_crc_reset <= 1'b0;
              end else begin
                _zz_io_crc_reset <= 1'b1;
              end
            end
          end
          if(sdio_clk) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
            end
          end
        end
        fsm_enumDef_dat_write : begin
          if(when_sdio_l619) begin
            if(sdio_clk) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                dat_o <= send_payload[31 : 28];
                if(io_bus_4bit) begin
                  send_payload <= (send_payload <<< 4);
                end else begin
                  send_payload <= (send_payload <<< 1);
                end
              end
            end
            if(clk_lo) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                send_remaining <= ($signed(send_remaining) - $signed(8'h01));
              end
            end
          end else begin
            if(when_sdio_l633) begin
              wait_remaining <= 8'h14;
            end else begin
              if(io_send_stream_valid) begin
                send_payload_trg <= (! send_payload_trg);
                send_payload <= io_send_stream_payload;
                send_remaining <= (io_bus_4bit ? 8'h07 : 8'h1f);
                block_remaining <= ($signed(block_remaining) - $signed(16'h0001));
              end
            end
          end
        end
        fsm_enumDef_dat_write_crc : begin
          if(when_sdio_l649) begin
            wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
            crc0 <= _zz_crc0;
            crc1 <= _zz_crc1;
            crc2 <= _zz_crc2;
            crc3 <= _zz_crc3;
            debug_flg <= 1'b1;
          end else begin
            if(when_sdio_l653) begin
              if(sdio_clk) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                  wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
                  dat_o[0] <= crc0[15];
                  dat_o[1] <= crc1[15];
                  dat_o[2] <= crc2[15];
                  dat_o[3] <= crc3[15];
                  crc0 <= {crc0[14 : 0],1'b1};
                  crc1 <= {crc1[14 : 0],1'b1};
                  crc2 <= {crc2[14 : 0],1'b1};
                  crc3 <= {crc3[14 : 0],1'b1};
                end
              end
              if(clk_lo) begin
                if(clk_edge) begin
                  sdio_clk <= (! sdio_clk);
                end
              end
            end else begin
              dat_rsp <= (~ 8'h0);
              wait_remaining <= 8'h0;
            end
          end
        end
        fsm_enumDef_dat_write_rsp : begin
          dat_oe <= 1'b0;
          if(when_sdio_l678) begin
            if(sdio_clk) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                wait_remaining <= ($signed(wait_remaining) - $signed(8'h01));
              end
            end
            if(clk_lo) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
              end
            end
            if(when_sdio_l683) begin
              crc_dat_ok <= (dat_rsp[6 : 4] == 3'b010);
              crc_dat_fail <= (dat_rsp[6 : 4] != 3'b010);
            end
          end else begin
            if(sdio_clk) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
                if(when_sdio_l691) begin
                  dat_rsp <= {dat_rsp[6 : 0],io_sdio_dat[0]};
                end else begin
                  if(when_sdio_l696) begin
                    wait_remaining <= 8'h06;
                  end
                end
              end
            end
            if(clk_lo) begin
              if(clk_edge) begin
                sdio_clk <= (! sdio_clk);
              end
            end
          end
        end
        fsm_enumDef_dat_write_wait : begin
          block_remaining <= ($signed(io_block_size) >>> 2);
          _zz_io_line_reset <= 1'b0;
          _zz_io_calc_en_1 <= 1'b1;
          crc_dat_ok <= 1'b0;
          crc_dat_fail <= 1'b0;
          send_remaining <= 8'hff;
          if(sdio_clk) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
              dat_oe <= 1'b1;
              dat_o <= 4'b0000;
            end
          end
          if(clk_lo) begin
            if(clk_edge) begin
              sdio_clk <= (! sdio_clk);
            end
          end
        end
        default : begin
        end
      endcase
      if(when_sdio_l365) begin
        wait_remaining <= 8'h7f;
        cmd_done <= 1'b0;
      end
    end
  end

  always @(posedge clk) begin
    send_payload_trg_regNext <= send_payload_trg;
    _zz_io_recv_stream_valid_1 <= _zz_io_recv_stream_valid;
    io_mmc_init_regNext_1 <= io_mmc_init;
  end

  always @(posedge clk) begin
    io_mmc_init_regNext <= io_mmc_init;
    io_cmd_en_regNext <= io_cmd_en;
    io_dat_next_en_regNext <= io_dat_next_en;
  end


endmodule

//sdio_crc16_3 replaced by sdio_crc16

//sdio_crc16_2 replaced by sdio_crc16

//sdio_crc16_1 replaced by sdio_crc16

module sdio_crc16 (
  input  wire          io_sdio_clk,
  input  wire          io_sdio_line,
  input  wire          io_calc_en,
  input  wire          io_line_reset,
  output wire [15:0]   io_line_crc16,
  input  wire          clk,
  input  wire          reset
);

  reg        [15:0]   crc;
  wire       [15:0]   polynomial;
  wire       [16:0]   crc_shift;
  wire       [15:0]   crc_calc;
  reg                 io_sdio_clk_regNext;
  wire                when_sdio_l53;

  assign polynomial = 16'h1021;
  assign crc_shift = {crc,1'b0};
  assign crc_calc = (crc_shift[15 : 0] ^ (crc[15] ? polynomial : 16'h0));
  assign io_line_crc16 = crc;
  assign when_sdio_l53 = ((io_sdio_clk && (! io_sdio_clk_regNext)) && io_calc_en);
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      crc <= 16'h0;
    end else begin
      if(io_line_reset) begin
        crc <= 16'h0;
      end else begin
        if(when_sdio_l53) begin
          crc <= (crc_calc[15 : 0] ^ (io_sdio_line ? polynomial : 16'h0));
        end
      end
    end
  end

  always @(posedge clk) begin
    io_sdio_clk_regNext <= io_sdio_clk;
  end


endmodule

module sdio_crc8 (
  input  wire          io_sdio_clk,
  input  wire [0:0]    io_sdio_line,
  input  wire          io_calc_en,
  input  wire          io_crc_reset,
  output wire [7:0]    io_crc_out,
  input  wire [7:0]    io_crc_in,
  input  wire          clk,
  input  wire          reset
);

  reg        [7:0]    crc;
  wire       [7:0]    polynomial;
  wire       [8:0]    crc_shift;
  wire       [7:0]    crc_calc;
  wire                crc_calc_signal;
  reg                 io_sdio_clk_regNext;
  wire                when_sdio_l110;

  assign polynomial = 8'h09;
  assign crc_shift = {io_crc_in,1'b0};
  assign crc_calc = crc_shift[7 : 0];
  assign crc_calc_signal = (crc_calc[7] ^ io_sdio_line[0]);
  assign io_crc_out = crc;
  assign when_sdio_l110 = ((io_sdio_clk && (! io_sdio_clk_regNext)) && io_calc_en);
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      crc <= 8'h0;
    end else begin
      if(io_crc_reset) begin
        crc <= 8'h0;
      end else begin
        if(when_sdio_l110) begin
          crc <= (crc_calc ^ (crc_calc_signal ? polynomial : 8'h0));
        end
      end
    end
  end

  always @(posedge clk) begin
    io_sdio_clk_regNext <= io_sdio_clk;
  end


endmodule
